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CY7C1415AV18 - (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture

Download the CY7C1415AV18 datasheet PDF. This datasheet also covers the CY7C1413AV18 variant, as both devices belong to the same (cy7c14xxav18) 36-mbit qdr-ii sram 4-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1413AV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1415BV18 (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
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Full PDF Text Transcription

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CY7C1411AV18, CY7C1426AV18 www.DataSheet4U.com CY7C1413AV18, CY7C1415AV18 36-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Functional Description The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support the read operations and the write port has dedicated data inputs to support the write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is through a common address bus.
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