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CY7C1382C Datasheet 18-Mb (512K x 36/1M x 18) Pipelined SRAM

Manufacturer: Cypress (now Infineon)

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General Description

[1] • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200,166 and 133MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.8 ns (for 225-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 166-MHz device) — 4.2 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1380C/CY7C1382C SRAM integ

Overview

CY7C1380C CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM.

Key Features

  • Functional.

📁 Similar Datasheet

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