CY7C1263V18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 300 MHz to 400 MHz clock for high bandwidth
- 4-Word Burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both read and write ports
- Read latency of 2.5 clock cycles
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed
- Single multiplexed address input bus latches address inputs