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CY7C1264XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

Download the CY7C1264XV18 datasheet PDF. This datasheet also covers the CY7C1262XV18 variant, as both devices belong to the same 36-mbit qdr ii+ xtreme sram two-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 450 MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed syst.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1262XV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1261V18 1.8V Synchronous Pipelined SRAM
CY7C1262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C1263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1263V18 1.8V Synchronous Pipelined SRAM
CY7C1263XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Full PDF Text Transcription

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CY7C1262XV18 CY7C1264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 450 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz ■ Available in 2.
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