CY7C1214F sram equivalent, 1-mb (32k x 32) flow-through sync sram.
* 32K X 32 common I/O
* 3.3V
–5% and +10% core power supply (VDD)
* 3.3V I/O supply (VDDQ)
* Fast clock-to-output times — 7.5 ns (117-MHz .
1]
The CY7C1214F is a 32,768 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is
Logic Block Diagram
A0, A1, A
ADDRESS REGISTER A[1:0]
MODE
ADV CLK
BURS.
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