CY7C1218F sram equivalent, 1-mb (32k x36) pipelined sync sram.
* Registered inputs and outputs for pipelined operation
* 32K × 36 common I/O architecture
* 3.3V core power supply
* 3.3V I/O operation
* Fast clock-.
and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1218F operates from a +3.3V core power supply while all outpu.
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