CY28358 buffer/driver equivalent, 200-mhz differential clock buffer/driver.
* Up to 200 MHz operation
* Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications
* Distributes one clock input to six diffe.
* Distributes one clock input to six differential outputs
* External feedback pin FBIN is used to synchronize th.
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential output levels. This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one fee.
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