CY28351 buffer/driver equivalent, differential clock buffer/driver.
* Supports 333-MHz and 400-MHz DDR SDRAM
* 60-
– 200-MHz operating frequency
* Phase-locked loop (PLL) clock distribution for double data rate.
* Distributes one clock input to ten differential outputs
* External feedback pin (FBIN) is used to synchronize .
This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels. This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feed.
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