CY7C1041G Datasheet | Cypress

Features - High speed - t AA = 10 ns / 15 ns - Embedded ECC for single-bit error correction[1] - Low active and standby currents - Active current: ICC = 38-m A typical - Standby current: ISB2 = 6-m A typical - Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V - 1.0-V data retention - TTL-patible inputs and outputs - Error indication (ERR) pin to indicate 1-bit error detection and correction - Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA packages Functional Description CY7C1041G and CY7C1041GE are high-performance CMOS fast static RAM devices with embedded ECC. Both devices are offered in single and dual chip-enable options and in multiple pin configurations. The CY7C1041GE device includes an ERR pin that signals an error-detection and correction event during a read cycle. Data writes are performed by asserting the Chip Enable (CE) and Write Enable (WE) inputs LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. Data reads are performed by asserting the Chip Enable (CE) and Output Enable (OE) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a high-impedance state during the following events: - The device is deselected (CE HIGH) - The control signals (OE, BLE, BHE) are de-asserted On the CY7C1041GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = HIGH)[1]. See the Truth Table on page 14 for a...