LTC6952 Datasheet | Analog Devices

FEATURES nn JESD204B/C, Subclass 1 SYSREF Signal Generation nn Low Noise Integer-N PLL nn Additive Output Jitter < 6fs RMS (Integration BW = 12k Hz to 20MHz, f = 4.5GHz) nn Additive Output Jitter 65fs RMS (ADC SNR Method) nn EZSync™, Parallel Sync™ Multichip Synchronization nn - 229d Bc/Hz Normalized In-Band Phase Noise Floor nn - 281d Bc/Hz Normalized In-Band 1/f Noise nn Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays nn Flexible Outputs Can Serve as Either a Device Clock or SYSREF Signal nn Reference Input Frequency up to 500MHz nn LTC6952Wizard™ Software Design Tool Support nn - 40ºC to 125°C Operating Junction Temperature Range APPLICATIONS nn High Performance Data Converter Clocking nn Wireless Infrastructure nn Test and Measurement DESCRIPTION The LTC®6952 is a high performance, ultralow jitter, JESD204B/C clock generation and distribution IC. It includes a Phase Locked Loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider. The LTC6952’s eleven outputs can be configured as up to five JESD204B/C subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply eleven general purpose clock outputs for non-JESD204B/C applications. Each output has its own individually programmable frequency divider and output driver. All outputs can also be synchronized and set to precise phase alignment using individual coarse half-cycle digital delays and fine analog time delays. For applications requiring more than eleven total outputs, multiple LTC6952s can be connected together using the EZSync or Parallel Sync synchronization protocols. All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 8319551 and 8819472. TYPICAL APPLICATION 3.3V 3.3V LTC6952Wizard REGISTER VALUES: FILE: LTC6952 EZSync STANDALONE 48.7Ω 33n F 48.7Ω 5V 22n...