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Motorola Electronic Components Datasheet

MC100ES6222 Datasheet

Low Voltage 1:15 Differential ECL/PECL Clock Divider and Fanout Buffer

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MC100ES6222 pdf
MOTOROLA
Freescale Semiconductor, Inc.
Order Number: MC100ES6222/D
SEMICONDUCTOR TECHNICAL DATA
Rev 1, 11/2002
www.DataSheet4U.com
Low Voltage 1:15 Differential
ECL/PECL Clock Divider and
Fanout Buffer
MC100ES6222
The Motorola MC100ES6222 is a bipolar monolithic differential clock
fanout buffer. Designed for most demanding clock distribution systems,
the MC100ES6222 supports various applications that require the
distribution of precisely aligned differential clock signals. Using SiGe
technology and a fully differential architecture, the device offers very low
skew outputs and superior digital signal characteristics. Target
applications for this clock driver is high performance clock distribution in
computing, networking and telecommunication systems.
LOW–VOLTAGE
1:15 DIFFERENTIAL
ECL/PECL CLOCK DIVIDER
AND FANOUT DRIVER
Features
15 differential ECL/PECL outputs (4 output banks)
2 selectable differential ECL/PECL inputs
Selectable ÷1 or ÷2 frequency divider
130 ps maximum device skew
Supports DC to 3 GHz input frequency
Single 3.3V, -3.3V, 2.5V or -2.5V supply
Standard 52 lead LQFP package with exposed pad for enhanced thermal
characteristics
Supports industrial temperature range
Pin and function compatible to the MC100EP222
TB SUFFIX
52–LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A
Functional Description
The MC100ES6222 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The
CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and
six differential clock output pairs can be independently configured to distribute the input frequency or ÷2 of the input frequency.
The FSELA, FSELB, FSELC, FSELD and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a
MR pulse for resynchronization of the the ÷2 outputs. For the functionality of the MR control input, see Figure 5. , “Functional
Diagram,” on page 7.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if
only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6222 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the
MC100ES6222 supports positive (PECL) and negative (ECL) supplies. The MC100ES6222 is pin and function compatible to the
MC100EP222.
© Motorola, Inc. 2002
For More Information On This Product,
Go to: www.freescale.com


Motorola Electronic Components Datasheet

MC100ES6222 Datasheet

Low Voltage 1:15 Differential ECL/PECL Clock Divider and Fanout Buffer

No Preview Available !

MC100ES6222 pdf
MC100ES6222
Freescale Semiconductor, Inc.
www.DataSheet4U.com
FSELA
CLK0
CLK0
VCC
CLK1
CLK1
VEE
VCC
VEE
0 ÷1
1 ÷2
CLK_SEL
VEE
FSELB
FSELC
MR
FSELD
VEE
VEE
VEE
VEE
0
1
0
1
0
1
0
1
QA0
QA1
QB0
VCC
QB1 QB2
QB2 QB2
QB1
QC0 QB1
QB0
QC1
QB0
QC2 VCC
QC3 QA1
QA1
QD0 QA0
QD1 QA0
VCC
QD2
QD3
QD4
QD5
VBB
39 38 37 36 35 34 33 32 31 30 29 28 27
40 26
41 25
42 24
43 23
44 22
45 21
46 MC100ES6222 20
47 19
48 18
49 17
50 16
51 15
52 14
1 2 3 4 5 6 7 8 9 10 11 12 13
QD0
QD0
QD1
QD1
QD2
QD2
QD3
QD3
QD4
QD4
QD5
QD5
VCC
Figure 1. MC100ES6222 Logic Diagram
Figure 2. 52–Lead Package Pinout (Top View)
Table 1. Function Table
Control Pin
FSELA (asynchronous)
FSELB (asynchronous)
FSELC (asynchronous)
FSELD (asynchronous)
CLK_SEL (asynchronous)
MR (asynchronous)
0
÷1
÷1
÷1
÷1
CLK0
Active
1
÷2
÷2
÷2
÷2
CLK1
Reset. QX = L and QX = H.
MOTOROLA
For More Informa2tion On This Product,
Go to: www.freescale.com
TIMING SOLUTIONS


Part Number MC100ES6222
Description Low Voltage 1:15 Differential ECL/PECL Clock Divider and Fanout Buffer
Maker Motorola
Total Page 12 Pages
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MC100ES6222 pdf
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