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Freescale Semiconductor Electronic Components Datasheet

MC100ES6221 Datasheet

Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer

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MC100ES6221 pdf
Freescale Semiconductor
Technical Data
Low Voltage 1:20 Differential
ECL/PECL/HSTL Clock Fanout Buffer
MC100ES6221
Rev 5, 04/2005
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MC100ES6221
The MC100ES6221 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6221
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver is high performance clock
distribution in computing, networking and telecommunication systems.
LOW VOLTAGE DUAL
1:20 DIFFERENTIAL ECL/PECL/HSTL
CLOCK FANOUT BUFFER
Features
• 1:20 differential clock fanout buffer
• 100 ps maximum device skew
• SiGe technology
• Supports DC to 2 GHz operation of clock or data signals
• ECL/PECL compatible differential clock outputs
• ECL/PECL/HSTL compatible differential clock inputs
• Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
• Standard 52 lead LQFP package with exposed pad for enhanced thermal
characteristics
• Supports industrial temperature range
• Pin and function compatible to the MC100EP221
• 52-lead Pb-free Package Available
Functional Description
TB SUFFIX
52-LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A-01
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 1336A-01
The MC100ES6221 is designed for low skew clock distribution systems and
supports clock frequencies up to 2 GHz. The device accepts two clock sources.
The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The
selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If VBB is connected to the CLK0 or CLK1 input
and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the
VBB bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6221 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6221 supports positive (PECL) and negative (ECL) supplies. The MC100ES6221 is pin and function compatible to the
MC100EP221.
© Freescale Semiconductor, Inc., 2005. All rights reserved.


Freescale Semiconductor Electronic Components Datasheet

MC100ES6221 Datasheet

Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer

No Preview Available !

MC100ES6221 pdf
CLK0
CLK0
VCC
CLK1
CLK1
VEE
VCC
VEE
CLK_SEL
VEE
0
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
••
••
••
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
VBB
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VCC 4039 38 37 36 35 34 33 32 31 30 29 28 27 26 Q12
Q5 41
25 Q12
Q5 42
24 Q13
Q4 43
23 Q13
Q4 44
Q3 45
MC100ES6221
22 Q14
21 Q14
Q3 46
20 Q15
Q2 47
19 Q15
Q2 48
18 Q16
Q1 49
17 Q16
Q1 50
16 Q17
Q0 51
15 Q17
Q0
52 14
1 2 3 4 5 6 7 8 9 10 11 12 13
VCC
Figure 1. MC100ES6221 Logic Diagram
Figure 2. 52-Lead Package Pinout (Top View)
Table 1. Pin Configuration
Pin I/O Type
Function
CLK0, CLK0
Input
ECL/PECL
Differential reference clock signal input
CLK1, CLK1
Input
HSTL
Alternative differential reference clock signal input
CLK_SEL
Input
ECL/PECL
Reference clock input select
QA[0–19], QA[0–19]
VEE(1)
VCC
Output
Supply
Supply
ECL/PECL
Differential clock outputs
Negative power supply
Positive power supply. All VCC pins must be connected to the positive
power supply for correct DC and AC operation.
VBB
Output
DC
Reference voltage output for single ended ECL and PECL operation
1. In ECL mode (negative power supply mode), VEE is either –3.3 V or –2.5 V and VCC is connected to GND (0 V). In PECL mode (positive
power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are
referenced to the most positive supply (VCC).
Table 2. Function Table
Pin
CLK_SEL
0
CLK0, CLK0 input pair is the reference clock. CLK0 can be
driven by ECL or PECL compatible signals.
1
CLK1, CLK1 input pair is the reference clock. CLK1 can be
driven by HSTL compatible signals.
MC100ES6221
2
Advanced Clock Drivers Devices
Freescale Semiconductor


Part Number MC100ES6221
Description Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Maker Freescale Semiconductor
Total Page 12 Pages
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