http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf



Integrated Device Technology Electronic Components Datasheet

ICS661 Datasheet

PRECISION AUDIO CLOCK SOURCE

No Preview Available !

ICS661 pdf
PRECISION AUDIO CLOCK SOURCE
DATASHEET
ICS661
Description
www.datasheet4u.com
The ICS661 provides synchronous clock generation for
audio sampling clock rates derived from an MPEG stream,
or can be used as a standalone clock source with a 27 MHz
crystal. The device uses the latest PLL technology to
provide excellent phase noise and long term jitter
performance for superior synchronization and S/N ratio.
Please contact IDT if you have a requirement for an input
and output frequency not included here - we can rapidly
modify this product to meet special requirements.
Features
Packaged in 16-pin TSSOP
Available in Pb (lead) fere package
Clock or crystal input
Low phase noise
Low jitter
Exact (0 ppm) multiplication ratios
Reference clock output available
Support for 256, 384, 512, and 768 times sampling rate
Block Diagram
X2
X1/REFIN
SELIN
S3:0 4
VDD (P2)
Crystal
Oscillator
VDD (P3) VDDO VDDR
REF
GND (P13)
PLL Clock
Synthesis
GND (P6) GND (P5)
CLK
IDT™ / ICS™ PRECISION AUDIO CLOCK SOURCE
1
ICS661
REV D 111804



Integrated Device Technology Electronic Components Datasheet

ICS661 Datasheet

PRECISION AUDIO CLOCK SOURCE

No Preview Available !

ICS661 pdf
ICS661
PRECISION AUDIO CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
X1/REFIN
www.datasheet4uV.cDoDm
VDD
S0
GND
GND
S3
S2
1
2
3
4
5
6
7
8
16 X2
15 REF
14 VDDR
13 GND
12 SELIN
11 VDDO
10 S1
9 CLK
16-pin 4.40 mil body, 0.50 mm pitch TSSOP
Pin Descriptions
Output Clock Selection Table
Input
Output
S3 S2 S1 S0 Frequency Frequency
(MHz)
(MHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
8.192
11.2896
12.288
24.576
12.288
16.9344
18.432
36.864
16.384
22.5792
24.576
49.152
24.576
33.8688
36.864
73.728
Pin Pin
Number Name
1 X1/REFIN
2 VDD
3 VDD
4 S0
5 GND
6 GND
7 S3
8 S2
9 CLK
10 S1
11 VDDO
12 SELIN
13 GND
14 VDDR
15 REF
16 X2
Pin
Type
Input
Power
Power
Input
Power
Power
Input
Input
Output
Input
Power
Input
Power
Power
Output
Input
Pin Description
Connect this pin to a crystal or clock input
Power supply for crystal oscillator.
Power supply for PLL.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Connect to ground.
Ground for output stage.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Clock output.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Power supply for output stage.
Low for clock input, high for crystal. On chip pull-up.
Connect to ground.
Power supply for reference output. Ground to turn off REF.
Reference clock output.
Connect this pin to a crystal. Leave open if using a clock input.
IDT™ / ICS™ PRECISION AUDIO CLOCK SOURCE
2
ICS661
REV D 111804



Integrated Device Technology Electronic Components Datasheet

ICS661 Datasheet

PRECISION AUDIO CLOCK SOURCE

No Preview Available !

ICS661 pdf
ICS661
PRECISION AUDIO CLOCK SOURCE
CLOCK SYNTHESIZER
Application Information
Series Termination Resistor
Clock output traces should use series termination. To series
wwtewr.mdaitnaashteeeat45u0.comtrace (a commonly used trace impedance),
place a 33resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20.
Decoupling Capacitors
As with any high performance mixed-signal IC, the ICS661
must be isolated from system power supply noise to perform
optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the ICS661
should use one common connection to the PCB power
plane as shown in the diagram on the next page. The ferrite
bead and bulk capacitor help reduce lower frequency noise
in the supply that can lead to output clock phase modulation.
Recommended Power Supply Connection for
Optimal Device Performance
Connection to 3.3V
Power Plane
Ferrite
Bead
VDD Pin
VDD Pin
Bulk Decoupling Capacitor
(such as 1 F Tantalum)
VDD Pin
0.01 F Decoupling Capacitors
capacitance of the board to match the nominally required
crystal load capacitance. To reduce possible noise pickup,
use very short PCB traces (and no vias) been the crystal
and device.
The value of the load capacitors can be roughly determined
by the formula C = 2(CL - 6) where C is the load capacitor
connected to X1 and X2, and CL is the specified value of the
load capacitance for the crystal. A typical crystal CL is 18 pF,
so C = 2(18 - 6) = 24 pF. Because these capacitors adjust
the stray capacitance of the PCB, check the output
frequency using your final layout to see if the value of C
should be changed.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted next to the device
with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI and obtain the best signal integrity, the
33series termination resistor should be placed close to
the clock output.
All power supply pins must be connected to the same
voltage, except VDDR and VDDO may be connected to a
lower voltage in order to change the output level. If the
reference output is not used, ground VDDR.
Crystal Load Capacitors
If a crystal is used, the device crystal connections should
include pads for capacitors from X1 to ground and from X2
to ground. These capacitors are used to adjust the stray
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS661. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
IDT™ / ICS™ PRECISION AUDIO CLOCK SOURCE
3
ICS661
REV D 111804




Part Number ICS661
Description PRECISION AUDIO CLOCK SOURCE
Maker Integrated Device Technology
Total Page 7 Pages
PDF Download
ICS661 pdf
Download PDF File
ICS661 pdf
View for Mobile






Related Datasheet

1 ICS660 Digital Video Clock Source Integrated Circuit Systems
Integrated Circuit Systems
ICS660 pdf
2 ICS661 Precision Audio Clock Source Integrated Circuit Systems
Integrated Circuit Systems
ICS661 pdf
3 ICS661 PRECISION AUDIO CLOCK SOURCE Integrated Device Technology
Integrated Device Technology
ICS661 pdf
4 ICS662-02 NTSC/PAL AUDIO CLOCK Integrated Circuit Systems
Integrated Circuit Systems
ICS662-02 pdf
5 ICS662-03 HDTV Audio/Video Clock Source Integrated Circuit Systems
Integrated Circuit Systems
ICS662-03 pdf
6 ICS662-03 HDTV AUDIO/VIDEO CLOCK SOURCE Integrated Device Technology
Integrated Device Technology
ICS662-03 pdf
7 ICS663 PLL BUILDING BLOCK Integrated Circuit Systems
Integrated Circuit Systems
ICS663 pdf
8 ICS664-01 Digital Video Clock Source Integrated Circuit Systems
Integrated Circuit Systems
ICS664-01 pdf
9 ICS664-02 PECL Digital Video Clock Source Integrated Circuit Systems
Integrated Circuit Systems
ICS664-02 pdf




Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components