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Cypress Semiconductor Electronic Components Datasheet

CY14B101K Datasheet

1 Mbit (128K x 8) nvSRAM

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CY14B101K pdf
PRELIMINARY
CY14B101K
1 Mbit (128K x 8) nvSRAM With Real-Time Clock
Features
• Data integrity of Cypress nvSRAM combined with full
featured Real-Time Clock (RTC)
• Watchdog timer
• Clock alarm with programmable interrupts
• Capacitor or battery backup for RTC
www.DataSheet4U2.c5onms, 35 ns, and 45 ns access times
• “Hands-off” automatic STORE on power down with only a
small capacitor
STORE to QuantumTrap™ initiated by software, device pin,
or on power down
RECALL to SRAM initiated by software or on power up
• Infinite READ, WRITE, and RECALL cycles
• High reliability
— Endurance to 200,000 cycles
Data retention: 20 years @55°C
• 10 mA typical ICC at 200 ns cycle time
• Single 3V operation +20%, –10%
• Commercial and industrial temperature
• SSOP package (ROHS compliant)
Logic Block Diagram
Functional Description
The Cypress CY14B101K combines a 1 Mbit nonvolatile static
RAM with a full featured real-time clock in a monolithic
integrated circuit. The embedded nonvolatile elements
incorporate QuantumTrap technology producing the world’s
most reliable nonvolatile memory. The SRAM can be read and
written an infinite number of times, while independent,
nonvolatile data resides in the nonvolatile elements.
The Real-Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy
oscillator. The alarm function is programmable for one time
alarm or periodic seconds, minutes, hours, or days. There is
also a programmable watchdog timer for process control.
A5
A6
A7
A8
A9
A 12
A 13
A 14
A 15
A 16
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
QuantumTrap
1024 x 1024
STORE
STATIC RAM
ARRAY
1024 X 1024
RECALL
COLUMN IO
COLUMN DEC
A 0 A1 A 2 A 3 A 4 A 10 A 11
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
VRTCbat
VRTCcap
HSB
SOFTWARE
DETECT
-A15 A0
RTC
MUX
x1
x2
INT
-A16 A0
OE
CE
WE
Cypress Semiconductor Corporation
Document #: 001-06401 Rev. *E
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised March 01, 2007
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Cypress Semiconductor Electronic Components Datasheet

CY14B101K Datasheet

1 Mbit (128K x 8) nvSRAM

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CY14B101K pdf
PRELIMINARY
CY14B101K
Pin Configurations
www.DataSheet4U.com
VCAP
A16
A14
A12
A7
A6
A5
INT
A4
NC
NC
NC
VSS
NC
VRTCbat
DQ0
A3
A2
A1
A0
DQ1
DQ2
x1
x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-SSOP
Top View
(Not To Scale)
48 VCC
47 A15
46 HSB
45 WE
44 A13
43 A8
42 A9
41 NC
40 A11
39 NC
38 NC
37 NC
36 VSS
35 NC
34 VRTCcap
33 DQ6
32 OE
31 A10
30 CE
29 DQ7
28 DQ5
27 DQ4
26 DQ3
25 VCC
Pin Definitions
Pin Name IO Type
Description
A0 – A16
Input
Address inputs used to select one of the 131,072 bytes of the nvSRAM.
DQ0 – DQ7 Input Output Bidirectional data IO lines. Used as input or output lines depending on operation
NC No Connect No Connects. This pin is not connected to the die
WE
Input
Write Enable Input, active LOW. When selected LOW, enables data on the IO pins to be written
to the address location latched by the falling edge of CE.
CE
Input
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, active LOW. The active low OE input enables the data output buffers during READ
cycles. Deasserting OE high causes the IO pins to tri-state.
X1
X2
VRTCcap
VRTCbat
INT
Output Crystal connection, drives crystal on start up.
Input
Crystal connection for 32.768 kHz crystal.
Power Supply Capacitor supplied backup RTC supply voltage. (Left unconnected if VRTCbat is used)
Power Supply Battery supplied backup RTC supply voltage. (Left unconnected if VRTCcap is used)
Output Interrupt Output. Program to respond to the clock alarm, the watchdog timer and the power monitor.
Programmable to either active HIGH (push/pull) or LOW (open drain).
VSS
VCC
HSB
VCAP
Ground Ground for the device. Must be connected to ground of the system.
Power Supply Power Supply inputs to the device.
Input Output Hardware Store Busy. When LOW this output indicates a Hardware Store is in progress. When
pulled low external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional).
Power Supply AutoStoreTM Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document #: 001-06401 Rev. *E
Page 2 of 24
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Cypress Semiconductor Electronic Components Datasheet

CY14B101K Datasheet

1 Mbit (128K x 8) nvSRAM

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CY14B101K pdf
PRELIMINARY
CY14B101K
Device Operation
The CY14B101K nvSRAM is made up of two functional
components paired in the same physical cell, a SRAM memory
cell and a nonvolatile QuantumTrap cell. The SRAM memory
cell operates as a standard fast static RAM. Transfer of the
data can be from the SRAM to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture allows all cells to be
stored and recalled in parallel. During the STORE and
RECALL operations SRAM READ and WRITE operations are
inhibited. The CY14B101K supports infinite reads and writes
just like a typical SRAM. In addition, it provides infinite
RECALL operations from the nonvolatile cells and up to
www.DataShee2t40U0.,c0o0m0 STORE operations.
SRAM READ
The CY14B101K performs a READ cycle whenever CE and
OE are low, while WE and HSB are high. The address
specified on pins A0-16 determines which of the 131,072 data
bytes will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay of tAA
(READ cycle 1). If the READ is initiated by CE or OE, the
outputs will be valid at tACE or at tDOE, whichever is later
(READ cycle 2). The data outputs repeatedly responds to
address changes within the tAA access time without the need
for transitions on any control input pins. It remains valid until
another address change, or until CE or OE is brought high, or
WE or HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable before
entering the WRITE cycle and must remain stable until either
CE or WE goes high, at the end of the cycle. The data on the
common IO pins DQ0–7 will be written into the memory if the
data is valid tSD before the end of a WE-controlled WRITE or
before the end of an CE-controlled WRITE. It is recommended
that OE be kept high during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left low,
internal circuitry turns off the output buffers tHZWE after WE
goes low.
AutoStore Operation
The CY14B101K stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store activated by HSB, Software Store activated by an
address sequence, and AutoStore on device power down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101K.
During normal operation, the device draws current from VCC
to charge a capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the VCC pin drops below VSWITCH,
the part automatically disconnects the VCAP pin from VCC. A
STORE operation will be initiated with power provided by the
VCAP capacitor.
Figure 1 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the Table , “DC
Electrical Characteristics,” on page 14 for the size of VCAP.
Figure 1. AutoStore Mode
VCAP
VCC
VCC
WE
The voltage on the VCAP pin is driven to 5V by a charge pump
internal to the chip. A pull up must be placed on WE to hold it
inactive during power up.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. Monitor the HSB signal by the system to detect if
an AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B101K provides the HSB pin for controlling and
acknowledging the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY14B101K conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM took place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven low to indicate a busy condition while the STORE
(initiated by any means) is in progress.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14B101K continues SRAM operations for
tDELAY. During tDELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
During any STORE operation, regardless of how it was
initiated, the CY14B101K continues to drive the HSB pin low,
releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY14B101K remains
disabled until the HSB pin returns high. Leave the HSB
unconnected if it is not used.
Document #: 001-06401 Rev. *E
Page 3 of 24
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Part Number CY14B101K
Description 1 Mbit (128K x 8) nvSRAM
Maker Cypress Semiconductor
Total Page 24 Pages
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