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Cypress Semiconductor Electronic Components Datasheet

CY14B101LA Datasheet

1-Mbit (128 K x 8/64 K x 16) nvSRAM

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CY14B101LA pdf
CY14B101LA
CY14B101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
20 ns, 25 ns, and 45 ns access times
Internally organized as 128 K × 8 (CY14B101LA) or 64 K × 16
(CY14B101NA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20% to –10% operation
Industrial temperature
Logic Block Diagram [1, 2, 3]
Packages
32-pin small-outline integrated circuit (SOIC)
44-/54-pin thin small outline package (TSOP) Type II
48-pin shrink small-outline package (SSOP)
48-ball fine-pitch ball grid array (FBGA)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 128 K bytes of 8 bits each or 64 K words
of 16 bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
For a complete list of related resources, click here.
Quatrum Trap
VCC
VCAP
1024 X 1024
A5
R
O
A6 W
STORE
POWER
CONTROL
A7
A8
A9
A12
RECALL
D
E
C STATIC RAM
STORE/RECALL
CONTROL
HSB
A13 O ARRAY
A14
A15
A16
D 1024 X 1024
E
R
SOFTWARE
DETECT
A14 - A2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I
N
P
U
T
B COLUMN I/O
U
F
F
E
R COLUMN DEC
S
A0 A1 A2 A3 A4 A10 A11
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-42879 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 12, 2014



Cypress Semiconductor Electronic Components Datasheet

CY14B101LA Datasheet

1-Mbit (128 K x 8/64 K x 16) nvSRAM

No Preview Available !

CY14B101LA pdf
CY14B101LA
CY14B101NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 5
Device Operation .............................................................. 6
SRAM Read ................................................................ 6
SRAM Write ................................................................. 6
AutoStore Operation .................................................... 6
Hardware STORE Operation ....................................... 6
Hardware RECALL (Power-up) ................................... 7
Software STORE ......................................................... 7
Software RECALL ....................................................... 7
Preventing AutoStore .................................................. 8
Data Protection ............................................................ 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads ................................................................ 11
AC Test Conditions ........................................................ 11
AC Switching Characteristics ....................................... 12
SRAM Read Cycle .................................................... 12
SRAM Write Cycle ..................................................... 12
Switching Waveforms .................................................... 12
AutoStore/Power-Up RECALL ....................................... 15
Switching Waveforms .................................................... 15
Software Controlled STORE/RECALL Cycle ................ 16
Switching Waveforms .................................................... 16
Hardware STORE Cycle ................................................. 17
Switching Waveforms .................................................... 17
Truth Table For SRAM Operations ................................ 18
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 20
Package Diagrams .......................................................... 21
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC Solutions ......................................................... 30
Document Number: 001-42879 Rev. *Q
Page 2 of 30



Cypress Semiconductor Electronic Components Datasheet

CY14B101LA Datasheet

1-Mbit (128 K x 8/64 K x 16) nvSRAM

No Preview Available !

CY14B101LA pdf
CY14B101LA
CY14B101NA
Pinouts
Figure 1. Pin Diagram – 44-pin TSOP II
NC
NC[7]
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 44-pin TSOP II 36
10 (× 8)
35
11
12 Top View
13 (not to scale)
14
34
33
32
31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
HSB
NC
NC[6]
[5]
NC
[4]
NC
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
VCAP
A14
A13
A12
A11
A10
NC
NC
A0 1
44
A1 2
43
A2 3
42
A3 4
41
A4 5
40
CE 6
39
DQ0 7
38
DQ1 8
37
DQ2 9 44-pin TSOP II 36
DQ3 10
(× 16)[8]
35
VCC 11
34
VSS
DQ4
12 Top View
13 (not to scale)
33
32
DQ5 14
31
DQ6 15
DQ7 16
30
29
WE 17
28
A5 18
A6 19
27
26
A7 20
25
A8 21
24
A9 22
23
Figure 2. Pin Diagram – 48-pin SSOP and 32-pin SOIC
VCAP
A16
A14
A12
A7
A6
A5
NC
A4
NC
NC
NC
VSS
NC
NC
DQ0
A3
A2
A1
A0
DQ1
DQ2
NC
NC
1
2
3
4
5
6
7
8
9
10
48-pin SSOP
11 (×8)
12 Top View
13 (not to scale)
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
A15
HSB
WE
A13
A8
A9
NC
A11
NC
NC
NC
VSS
NC
NC
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
Notes
4. Address expansion for 2-Mbit. NC pin not connected to die.
5. Address expansion for 4-Mbit. NC pin not connected to die.
6. Address expansion for 8-Mbit. NC pin not connected to die.
7. Address expansion for 16-Mbit. NC pin not connected to die.
8. HSB pin is not available in 44-pin TSOP II (× 16) package.
32-pin SOIC
((x×88))
Top View
(not to scale)
NC [5]
NC [4]
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
Document Number: 001-42879 Rev. *Q
Page 3 of 30




Part Number CY14B101LA
Description 1-Mbit (128 K x 8/64 K x 16) nvSRAM
Maker Cypress Semiconductor
Total Page 30 Pages
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