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Analog Devices Semiconductor Electronic Components Datasheet

AD5312 Datasheet

+2.5 V to +5.5 V/ 230 uA Dual Rail-to-Rail/ Voltage Output 8-/10-/12-Bit DACs

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AD5312 pdf
a +2.5 V to +5.5 V, 230 A Dual Rail-to-Rail,
Voltage Output 8-/10-/12-Bit DACs
AD5302/AD5312/AD5322*
FEATURES
AD5302: Two 8-Bit Buffered DACs in One Package
AD5312: Two 10-Bit Buffered DACs in One Package
AD5322: Two 12-Bit Buffered DACs in One Package
10-Lead SOIC Package
Micropower Operation: 300 A @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.5 V to +5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design Over All Codes
Buffered/Unbuffered Reference Input Options
0–VREF Output Voltage
Power-On-Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5302/AD5312/AD5322 are dual 8-, 10- and 12-bit buff-
ered voltage output DACs in a 10-lead µSOIC package that
operate from a single +2.5 V to +5.5 V supply consuming
230 µA at 3 V. Their on-chip output amplifiers allow the outputs
to swing rail-to-rail with a slew rate of 0.7 V/µs. The AD5302/
AD5312/AD5322 utilize a versatile 3-wire serial interface which
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™ and DSP interface
standards.
The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs may be configured as
buffered or unbuffered inputs. The outputs of both DACs may
be updated simultaneously using the asynchronous LDAC in-
put. The parts incorporate a power-on-reset circuit that ensures
that the DAC outputs power-up to 0 V and remain there until a
valid write takes place to the device. The parts contain a power-
down feature that reduces the current consumption of the
devices to 200 nA at 5 V (50 nA at 3 V) and provides software-
selectable output loads while in power-down mode.
The low power consumption of these parts in normal operation
make them ideally suited to portable battery operated equip-
ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at
3 V, reducing to 1 µW in power-down mode.
POWER-ON
RESET
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFA
AD5302/AD5312/AD5322
SYNC
SCLK
DIN
INPUT
REGISTER
INTERFACE
LOGIC
DAC
REGISTER
STRING
DAC
BUFFER
POWER-DOWN
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
BUFFER
VOUTA
RESISTOR
NETWORK
VOUTB
RESISTOR
NETWORK
LDAC
VREFB
GND
*Patent Pending; protected by U.S. Patent No. 5684481.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999


Analog Devices Semiconductor Electronic Components Datasheet

AD5312 Datasheet

+2.5 V to +5.5 V/ 230 uA Dual Rail-to-Rail/ Voltage Output 8-/10-/12-Bit DACs

No Preview Available !

AD5312 pdf
AD5302/AD5312/AD5322–SPECIFICATIONS (VDD = +2.5 V to +5.5 V; VREF = +2 V; RL = 2 k
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
Parameter1
B Version2
Min Typ
Max
Units
Conditions/Comments
DC PERFORMANCE3, 4
AD5302
Resolution
Relative Accuracy
Differential Nonlinearity
AD5312
Resolution
Relative Accuracy
Differential Nonlinearity
AD5322
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
Offset Error Drift5
Gain Error Drift5
Power Supply Rejection Ratio5
DC Crosstalk5
8
± 0.15
± 0.02
10
± 0.5
± 0.05
12
±2
± 0.2
± 0.4
± 0.15
10
–12
–5
–60
30
±1
± 0.25
±3
± 0.5
± 12
±1
±3
±1
60
Bits
LSB
LSB Guaranteed Monotonic by Design Over All Codes
Bits
LSB
LSB Guaranteed Monotonic by Design Over All Codes
Bits
LSB
LSB
% of FSR
% of FSR
mV
ppm of FSR/°C
ppm of FSR/°C
dB
µV
Guaranteed Monotonic by Design Over All Codes
See Figures 2 and 3
See Figures 2 and 3
See Figures 2 and 3
VDD = ± 10%
DAC REFERENCE INPUTS5
VREF Input Range
VREF Input Impedance
Reference Feedthrough
Channel-to-Channel Isolation
1
VDD
V
0
VDD
V
>10 M
180 k
–90 dB
–80 dB
Buffered Reference Mode
Unbuffered Reference Mode
Buffered Reference Mode
Unbuffered Reference Mode, Input Impedance = RDAC
Frequency = 10 kHz
Frequency = 10 kHz
OUTPUT CHARACTERISTICS5
Minimum Output Voltage6
Maximum Output Voltage6
DC Output Impedance
Short Circuit Current
Power-Up Time
LOGIC INPUTS5
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
0.001
VDD – 0.001
0.5
50
20
2.5
5
2.4
2.1
2.0
2
±1
0.8
0.6
0.5
3.5
V min
V max
mA
mA
µs
µs
µA
V
V
V
V
V
V
pF
This is a measure of the minimum and maximum
drive capability of the output amplifier.
VDD = +5 V
VDD = +3 V
Coming Out of Power-Down Mode. VDD = +5 V
Coming Out of Power-Down Mode. VDD = +3 V
VDD = +5 V ± 10%
VDD = +3 V ± 10%
VDD = +2.5 V
VDD = +5 V ± 10%
VDD = +3 V ± 10%
VDD = +2.5 V
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = +4.5 V to +5.5 V
VDD = +2.5 V to +3.6 V
IDD (Full Power-Down)
VDD = +4.5 V to +5.5 V
VDD = +2.5 V to +3.6 V
2.5
300
230
0.2
0.05
5.5
450
350
1
1
V
µA
µA
µA
µA
IDD Specification Is Valid for All DAC Codes
Both DACs Active and Excluding Load Currents
Both DACs in Unbuffered Mode. VIH = VDD and
VIL = GND. In Buffered Mode, extra current is
typically x µA per DAC where x = 5 µA + VREF/RDAC.
NOTES
1See Terminology.
2Temperature range: B Version: –40°C to +105°C.
3DC specifications tested with the outputs unloaded.
4Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).
5Guaranteed by design and characterization, not production tested.
6In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage,
VREF = VDD and “Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
–2– REV. 0


Part Number AD5312
Description +2.5 V to +5.5 V/ 230 uA Dual Rail-to-Rail/ Voltage Output 8-/10-/12-Bit DACs
Maker Analog Devices
Total Page 16 Pages
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