MT49H8M36 - 8 Meg x 36 x 8 Banks CIO RLDRAM 2
· 31 Hits Features • 533 MHz DDR operation (1.067 Gb/s/pin data rate) • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • Organization – 32 Meg x 9, ...MT46V8M16 - (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM
· 13 Hits c . U 4 t Double Data Rate (DDR) SDRAM e e8 Meg x 4 x 4 Banks MT46V32M4h – S – 4 Meg x 8 x 4 Banks MT46V16M8 a MT46V8M16 at – 2 Meg x 16 x 4 Banks .D ...MT48LC8M16A2 - 2 Meg x 16 x 4 Banks SDR SDRAM
· 6 Hits Features • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal, pipelined operation; ...MT46V4M32 - DOUBLE DATA RATE DDR SDRAM
· 6 Hits w w w • VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data cap...MT42L256M32D2 - Mobile LPDDR2 SDRAM
· 5 Hits Mobile LPDDR2 SDRAM MT42L256M16D1, MT42L128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4, MT42L384M32D3 Features ...MT48LC16M8A2 - 4 Meg x 8 x 4 Banks SDR SDRAM
· 5 Hits Features • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal, pipelined operation; ...MT48V8M16LFF4 - (MT48xxxMxxLFFx) SYNCHRONOUS DRAM
· 5 Hits • Temperature Compensated Self Refresh (TCSR) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operat...MT46H32M32LF - Mobile Low-Power DDR SDRAM
· 5 Hits Mobile Low-Power DDR SDRAM MT46H64M16LF – 16 Meg x 16 x 4 banks MT46H32M32LF – 8 Meg x 32 x 4 banks MT46H32M32LG – 8 Meg x 32 x 4 banks Features • VD...MT42L128M16D1 - Mobile LPDDR2 SDRAM
· 5 Hits Mobile LPDDR2 SDRAM MT42L128M16D1, MT42L64M32D1, MT42L64M64D2, MT42L128M32D2, MT42L256M32D4, MT42L128M64D4 MT42L96M64D3, MT42L192M32D3 Features • Ult...MT41K1G4 - DDR3L SDRAM
· 5 Hits • VDD = VDDQ = 1.35V (1.283–1.45V) • Backward compatible to VDD = VDDQ = 1.5V ±0.075V – Supports DDR3L devices to be backward compatible in 1.5V appli...MT48LC32M4A2 - 8 Meg x 4 x 4 Banks SDR SDRAM
· 4 Hits Features • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal, pipelined operation; ...MT4C1M16E5 - EDO DRAM
· 4 Hits • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages • High-performance CMOS silicon-gate process • Single power supply (+3.3V ...