Flip-Flop Datasheet | Pinout, Features, Price Comparison & PDF

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D

74HC574 Octal 3−State Noninverting D Flip−Flop High−Performance Silicon−Gate CMOS The 74HC574 is identical in pinout to the LS574. The device inputs a

HD74HC114 Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Description This flip-flop is edge sensitive to the clock input and change

74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 7 — 4 March 2016 Product data sheet 1. General description The 74HC

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dua

TC4013BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4013BP, TC4013BF TC4013B Dual D-Type Flip Flop TC4013B contains two independ

M54HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR . . . . . . . . HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.)

5476 DM5476 DM7476 Dual Master-Slave J-K Flip-Flops with Clear Preset and Complementary Outputs June 1989 5476 DM5476 DM7476 Dual Master-Slave J-K F

DATASHEET CD40174BMS CMOS Hex ‘D’-Type Flip-Flop Rev X.00 Jan 13, 2017 Features • High Voltage Type (20V Rating) • 5V, 10V and 15V Parametric Ratin

M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC =

CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop October 1987 Revised July 1999 CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad

Корпус: DIP-14 Микросхема К561ТМ2 представляет собой два двухступенчатых (master-slave) D-триггера со входами асинхронной установки и сброса и против

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS

CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad D Flip-Flop February 1988 CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0

SN74LS74A Dual D−Type Positive Edge−Triggered Flip−Flop The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high sp

TC74HC74AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic www.DataSheet4U.com TC74HC74AP,TC74HC74AF,TC74HC74AFN Dual D-Type Flip F

54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74

CD40175BMS December 1992 CMOS Quad ‘D’ Type Flip-Flop Pinout CD40175BMS TOP VIEW Features • High Voltage Type (20V Rating) • Output Compatible with

CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad D Flip-Flop February 1988 CD40174BM CD40174BC Hex D Flip-Flop CD40175BM CD40175BC Quad