CY7C1148V18
Cypress (now Infineon)
(CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
(CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
72Mb SigmaDDR-IIIe Burst of 2 ECCRAM
72Mb SigmaDDR-IIIe Burst of 2 ECCRAM
4G Bits Die DDRIII SDRAM
Complete DDR / DDRII and DDRIII Memory Solution Synchronous Buck PWM Controller
72Mb SigmaDDR-IIIe Burst of 2 ECCRAM
72Mb SigmaDDR-IIIe Burst of 2 ECCRAM
18Mb DDR-IIP CIO SYNCHRONOUS SRAM
18-Mbit DDR II+ SRAM Two-Word Burst Architecture
8M x 16 Bit x 8 Banks DDR II SDRAM
72Mb SigmaDDR-II Burst of 4 SRAM
2A DDR I/II/III Bus Termination Regulator
(CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
(CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
36Mb SigmaCIO DDR-II Burst SRAM
36Mb SigmaCIO DDR-II Burst SRAM
18Mb Pipelined DDRII SRAM
Complete DDRII/DDRIII/Low-Power DDRIII/DDRIV Memory Power Supply Controller
DDR-II SDRAM
72Mb DDR-IIP CIO SYNCHRONOUS SRAM