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A62S7308B Series Preliminary 128K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0

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® LY62L1024 Rev. 1.2 128K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Revised Icc De

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September 2004 Preliminary Information ® AS9C25256M2036L AS9C25128M2036L www.DataSheet4U.com 2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V

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September 2004 Preliminary Information ® AS9C25256M2036L AS9C25128M2036L www.DataSheet4U.com 2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V

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White Electronic Designs EDI88128C 128Kx8 MONOLITHIC SRAM, SMD 5962-89598 FEATURES „ Access Times of 70, 85, 100ns „ Available with Single Chip Sel

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Features • Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV) • Fast Read Access Time – 70 ns • Internal Program Control and Timer •

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March 2001 ® AS7C33128PFD32A AS7C33128PFD36A 3.3V 128K × 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words × 32 or 36 bit

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Features • Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV) • Fast Read Access Time – 70 ns • Internal Program Control and Timer •

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A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary Document Title 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM

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C8051F96x Ultra Low Power 128K, LCD MCU Family Ultra Low Power Consumption at 3.6 V - 130 µA/MHz Low-Power Active mode with dc-dc enabled - 120 nA s

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M29F010B 1 Mbit (128Kb x8, Uniform Block) Single Supply Flash Memory PRELIMINARY DATA s SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPER

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April 2005 ® AS7C33128NTD18B 3.3V 128K×18 Pipelined SRAM with NTDTM Features • Organization: 131,072 words × 18 bits • NTD™ architecture for efficie

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March 2002 ® AS7C33128PFS32A AS7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words × 32 or 36 bit

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ACT–SF2816 High Speed 128Kx16 SRAM / 512Kx16 FLASH Multichip Module FEATURES CIRCUIT TECHNOLOGY www.aeroflex.com I 2 – 128K x 8 SRAMs & 2 – 512K x

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December 2002 AS7C33128NTD32A AS7C33128NTD36A Š 9  .î  65$0 ZLWK 17'TM Features • Organization: 131,072 words × 32 or 36 bits NTD™1 archit

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Features • Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV) • Fast Read Access Time – 70 ns • Internal Program Control and Timer •

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Features • Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV) • Fast Read Access Time – 70 ns • Internal Program Control and Timer •

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CY7C1351G 4-Mbit (128K × 36) Flow-Through SRAM with NoBL™ Architecture 4-Mbit (128K × 36) Flow-Through SRAM with NoBL™ Architecture Features ■ Can su

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CY7C4281 CY7C4291 64K/128K x 9 Deep Sync FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memories • 64K × 9 (CY7C4281) • 128K × 9

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