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74HCT193 - Presettable synchronous 4-bit binary up/down counter

Download the 74HCT193 datasheet PDF. This datasheet also covers the 74HC193 variant, as both devices belong to the same presettable synchronous 4-bit binary up/down counter family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter.

Separate up/down clocks, CPU and CPD respectively, simplify operation.

The outputs change state synchronously with the LOW-to-HIGH transition of either clock input.

Features

  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Input levels:.
  • For 74HC193: CMOS level.
  • For 74HCT193: TTL level.
  • Synchronous reversible 4-bit binary counting.
  • Asynchronous parallel load.
  • Asynchronous reset.
  • Expandable without external logic.
  • Complies with JEDEC standards:.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC193-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT193
Manufacturer Nexperia
File Size 326.02 KB
Description Presettable synchronous 4-bit binary up/down counter
Datasheet download datasheet 74HCT193 Datasheet

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Full PDF Text Transcription

Click to expand full text
74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Rev. 7 — 8 September 2021 Product data sheet 1. General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL).
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