Download the 74HCT173 datasheet PDF.
This datasheet also covers the 74HC173 variant, as both devices belong to the same quad d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.
General Description
The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop.
Key Features
Complies with JEDEC standard no. 7A.
Input levels:.
For 74HC173: CMOS level.
For 74HCT173: TTL level.
Gated input enable for hold (do nothing) mode.
Gated output enable control mode.
Edge-triggered D-type register.
Asynchronous master reset.
ESD protection:.
HBM JESD22-A114F exceeds 2000 V.
MM JESD22-A115-A exceeds 200 V.
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering.
Full PDF Text Transcription for 74HCT173 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
74HCT173. For precise diagrams, tables, and layout, please refer to the original PDF.
74HC173; 74HCT173 Quad D-type flip-flop; positive-edge trigger; 3-state Rev. 4 — 25 January 2021 Product data sheet 1. General description The 74HC173; 74HCT173 is a quad...
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duct data sheet 1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of cloc
74HCT173 Datasheet
