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74AUP3G34 - Low-power triple buffer

Description

The 74AUP3G34 is a triple buffer.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • High noise immunity.
  • Low static power consumption; ICC = 0.9 μA (maximum).
  • Latch-up performance exceeds 100 mA per JESD 78B Class II.
  • Inputs accept voltages up to 3.6 V.
  • Low noise overshoot and undershoot < 10 % of VCC.
  • IOFF circuitry provides partial Power-down mode operation.
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65.

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Full PDF Text Transcription

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74AUP3G34 Low-power triple buffer Rev. 5 — 24 June 2022 Product data sheet 1. General description The 74AUP3G34 is a triple buffer. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • High noise immunity • Low static power consumption; ICC = 0.9 μA (maximum) • Latch-up performance exceeds 100 mA per JESD 78B Class II • Inputs accept voltages up to 3.
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