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74ALVCH16952DGG - 16-bit registered transceiver

Download the 74ALVCH16952DGG datasheet PDF. This datasheet also covers the 74ALVCH16952 variant, as both devices belong to the same 16-bit registered transceiver family and are provided as variant models within a single manufacturer datasheet.

Description

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver.

Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses.

Features

  • CMOS low-power consumption.
  • Multibyte flow-through pinout architecture.
  • Low inductance, multiple center power and ground pins for minimum noise and ground bounce.
  • Direct interface with TTL levels.
  • Output drive capability 50 Ω transmission lines at 85 °C.
  • Complies with JEDEC standard JESD8-B 3 Ordering information Table 1. Ordering information Type number Package Temperature range 74ALVCH16952DGG -40 °C to +85 °C Name TSSOP56 Descrip.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ALVCH16952-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74ALVCH16952 16-bit registered transceiver NXP
74ALVCH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver Fairchild Semiconductor
74ALVCH162244 16-bit buffer/line driver NXP
74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver Fairchild Semiconductor
74ALVCH162244 3.3V CMOS 16-BIT BUFFER/DRIVER Renesas

Other Datasheets by nexperia

Part Number Description
74ALVCH16952 16-bit registered transceiver
74ALVCH162244 16-bit buffer/line driver
74ALVCH162244DGG 16-bit buffer/line driver
74ALVCH162245 16-bit bus transceiver
74ALVCH16244 16-bit buffer/line driver

Full PDF Text Transcription

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74ALVCH16952 16-bit registered transceiver; 3-state Rev. 3 — 9 January 2018 Product data sheet 1 General description The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.
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