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74AHCT595D - 8-bit serial-in/serial-out or parallel-out shift register

Download the 74AHCT595D datasheet PDF. This datasheet also covers the 74AHC595 variant, as both devices belong to the same 8-bit serial-in/serial-out or parallel-out shift register family and are provided as variant models within a single manufacturer datasheet.

Description

The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Wide supply voltage range from 2.0 V to 5.5 V.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger action.
  • Overvoltage tolerant inputs to 5.5 V.
  • High noise immunity.
  • CMOS low power dissipation.
  • Input levels:.
  • The 74AHC595 operates with CMOS input levels.
  • The 74AHCT595 operates with TTL input levels.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC595-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74AHCT595D
Manufacturer Nexperia
File Size 289.71 KB
Description 8-bit serial-in/serial-out or parallel-out shift register
Datasheet download datasheet 74AHCT595D Datasheet

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Full PDF Text Transcription

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74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches Rev. 6 — 26 May 2020 Product data sheet 1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.
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