Click to expand full text
74AHC595-Q100;
74AHCT595-Q100
8-bit serial-in/serial-out or parallel-out shift register with
output latches
Rev. 2 — 26 May 2020
Product data sheet
1. General description
The 74AHC595-Q100; 74AHCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.
74AHC595-Q100 Datasheet
