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74AHC595T16 - 8-BIT SHIFT REGISTER

Download the 74AHC595T16 datasheet PDF. This datasheet also covers the 74AHC595 variant, as both devices belong to the same 8-bit shift register family and are provided as variant models within a single manufacturer datasheet.

Description

The 74AHC595 is an advanced high speed CMOS device.

An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP).

When asserted low the reset function (MR) sets all shift register values to zero and is independent of all clocks.

Features

  • Wide Supply Voltage Range from 2.0 V to 5.5V.
  • Sinks or sources 8mA at VCC = 4.5V.
  • CMOS low power consumption.
  • Schmitt Trigger Action at All Inputs.
  • Inputs Accept up to 5.5V.
  • ESD Protection Tested per JESD 22.
  • Exceeds 200-V Machine Model (A115-A).
  • Exceeds 2000-V Human Body Model (A114-A).
  • Exceeds 1000-V Charged Device Model (C101C).
  • Latch-Up Exceeds 250mA per JESD 78, Class II.
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2).
  • Hal.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC595-Diodes.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74AHC595 8-bit serial-in/serial or parallel-out shift register NXP
74AHC595 8-bit serial-in/serial-out or parallel-out shift register nexperia
74AHC595-Q100 8-bit serial-in/serial-out or parallel-out shift register nexperia
74AHC595BQ 8-bit serial-in/serial-out or parallel-out shift register nexperia
74AHC595D 8-bit serial-in/serial-out or parallel-out shift register nexperia

Other Datasheets by Diodes Incorporated

Part Number Description
74AHC595 8-BIT SHIFT REGISTER
74AHC595S16 8-BIT SHIFT REGISTER
74AHC594 8-BIT SHIFT REGISTER
74AHC00 QUADRUPLE 2-INPUT NAND GATES
74AHC00S14 QUADRUPLE 2-INPUT NAND GATES

Full PDF Text Transcription

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74AHC595 8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER Description The 74AHC595 is an advanced high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is independent of all clocks. Data from the input serial shift register is placed in the output register with a rising pulse on the storages resister clock (SHCP). With the output enable (OEሻ asserted low the 3-state outputs Q0-Q7 become active and present. All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together, the input shift register is always one clock cycle ahead of the output register.
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