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74AHC574D - Octal D-type flip-flop

Download the 74AHC574D datasheet PDF. This datasheet also covers the 74AHC574 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no.

7A.

Features

  • I Balanced propagation delays I All inputs have a Schmitt-trigger action I 3-state non-inverting outputs for bus orientated.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC574-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74AHC574 Octal D-type flip-flop NXP
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Other Datasheets by Nexperia

Part Number Description
74AHC574 Octal D-type flip-flop
74AHC574BQ Octal D-type flip-flop
74AHC574PW Octal D-type flip-flop
74AHC573 Octal D-type transparant latch
74AHC573-Q100 Octal D-type transparant latch

Full PDF Text Transcription

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74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 24 January 2008 Product data sheet 1. General description The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are available at the outputs.
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