Datasheet4U Logo Datasheet4U.com

74AHC594 - 8-bit shift register

Description

The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7A.

Features

  • s s s s s s Wide supply voltage range from 2.0 V to 5.5 V 8-bit serial-in, parallel-out shift register with storage Independent direct overriding clears on shift and storage registers Independent clocks for shift and storage registers Latch-up performance exceeds 100 mA per JESD 78 Class II Input levels: x CMOS levels: 74AHC594 only x TTL levels: 74AHCT594 only s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Specified from.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74AHC594 8-bit shift register nexperia
74AHC594 8-BIT SHIFT REGISTER Diodes
74AHC594-Q100 8-bit shift register nexperia
74AHC595 8-bit serial-in/serial-out or parallel-out shift register nexperia
74AHC595 8-BIT SHIFT REGISTER Diodes

Other Datasheets by NXP Semiconductors

Part Number Description
74AHC595 8-bit serial-in/serial or parallel-out shift register
74AHC541 Octal buffer/line driver
74AHC573 Octal D-type transparent latch
74AHC574 Octal D-type flip-flop
74AHC00 Quad 2-input NAND gate

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com 74AHC594; 74AHCT594 8-bit shift register with output register Rev. 01 — 4 July 2006 Product data sheet 1. General description The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered.
Published: |