Download the 74AHC138BQ datasheet PDF.
This datasheet also covers the 74AHC138 variant, as both devices belong to the same 3-to-8 line decoder/demultiplexer family and are provided as variant models within a single manufacturer datasheet.
General Description
The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard No.
7A.
Key Features
Balanced propagation delays.
All inputs have Schmitt-trigger action.
Demultiplexing capability.
Multiple input enable for easy expansion.
Ideal for memory chip select decoding.
Inputs accepts voltages higher than VCC.
For 74AHC138 only: operates with CMOS input levels.
For 74AHCT138 only: operates with TTL input levels.
Full PDF Text Transcription for 74AHC138BQ (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
74AHC138BQ. For precise diagrams, and layout, please refer to the original PDF.
74AHC138; 74AHCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 5 — 10 September 2020 Product data sheet 1. General description The 74AHC138; 74AHCT138 are high-spe...
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data sheet 1. General description The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected. There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
74AHC138BQ Datasheet
