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74AHC138T16 - 3-TO-8 LINE DECODER DEMULTIPLEXER

Download the 74AHC138T16 datasheet PDF. This datasheet also covers the 74AHC138 variant, as both devices belong to the same 3-to-8 line decoder demultiplexer family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC138 is an advanced high speed CMOS device.

The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaining seven being high.

Key Features

  • Wide Supply Voltage Range from 2.0 V to 5.5 V.
  • Sinks or sources 8mA at Vcc = 4.5V.
  • CMOS low power consumption.
  • Schmitt Trigger Action at All Inputs.
  • Inputs accept up to 5.5 V.
  • ESD Protection Tested per JESD 22 Exceeds 200-V Machine Model (A115-A) Exceeds 2000-V Human Body Model (A114-A) Exceeds 1000-V Charged Device Model (C101C).
  • Latch-Up Exceeds 250mA per JESD 78, Class II.
  • SO16 Available in “Green” Molding Compound (no B.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC138-Diodes.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for 74AHC138T16 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 74AHC138T16. For precise diagrams, and layout, please refer to the original PDF.

Preliminary 74AHC138 3-TO-8 LINE DECODER DEMULTIPLEXER Description Pin Assignments The 74AHC138 is an advanced high speed CMOS device. The device accepts a three bit bina...

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n advanced high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaining seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E 1 and E 2 asserted low and E3 asserted high. The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter. Features •

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