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SN74LVC1G80 - Single Positive-Edge-Triggered D-Type Flip-Flop

Description

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse.

Features

  • 1 Available in the Texas Instruments NanoFree™ Package.
  • Supports 5-V VCC Operation.
  • Inputs Accept Voltages to 5.5 V.
  • Supports Down Translation to VCC.
  • Maximum tpd of 4.2 ns at 3.3 V.
  • Low Power Consumption, 10-µA Maximum ICC.
  • ±24-mA Output Drive at 3.3 V.
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection.
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
  • ESD Protection.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC1G80 SCES221S – APRIL 1999 – REVISED NOVEMBER 2016 SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop 1 Features •1 Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Maximum tpd of 4.2 ns at 3.3 V • Low Power Consumption, 10-µA Maximum ICC • ±24-mA Output Drive at 3.
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