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SN74LVC1G34 - Single Buffer Gate

Description

This single buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G34 device performs the Boolean function Y = A in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC Operating range.

Features

  • 1 Available in the Ultra Small 0.64-mm2 Package (DPW) with 0.5-mm Pitch.
  • Supports 5-V VCC Operation.
  • Inputs Accept Voltages to 5.5 V.
  • Provides Down Translation to VCC.
  • Max tpd of 3.5 ns at 3.3 V.
  • Low Power Consumption, 1-μA Max ICC.
  • ±24-mA Output Drive at 3.3 V.
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection.
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
  • ESD Pr.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC1G34 SCES519M – DECEMBER 2003 – REVISED APRIL 2016 SN74LVC1G34 Single Buffer Gate 1 Features •1 Available in the Ultra Small 0.64-mm2 Package (DPW) with 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max tpd of 3.5 ns at 3.3 V • Low Power Consumption, 1-μA Max ICC • ±24-mA Output Drive at 3.
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