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SN74LVC1G125 - Single Bus Buffer Gate

General Description

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G125 device is a single line driver with a 3-state output.

The output is disabled when the output-enable (OE) input is high.

Key Features

  • 1 Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch.
  • Supports 5-V VCC Operation.
  • Inputs Accept Voltages to 5.5 V.
  • Provides Down Translation to VCC.
  • Max tpd of 3.7 ns at 3.3 V.
  • Low Power Consumption, 10-μA Max ICC.
  • ±24-mA Output Drive at 3.3 V.
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection.
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
  • ESD P.

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Other Datasheets by Texas Instruments

Part Number Description
SN74LVC1G125-EP Single Bus Buffer Gate
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SN74LVC1G126 Single Bus Buffer Gate
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC1G125 SCES223T – APRIL 1999 – REVISED OCTOBER 2014 SN74LVC1G125 Single Bus Buffer Gate With 3-State Output 1 Features •1 Available in the Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max tpd of 3.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.