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SN74AUP1G125 - Low-Power Single Bus Buffer Gate

Description

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output.

The output is disabled when the output-enable (OE) input is high.

This device has the input-disable feature, which allows floating input signals.

Features

  • 1 Available in the Texas Instruments NanoStar™ Package.
  • Low Static-Power Consumption (ICC = 0.9 µA Maximum).
  • Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V).
  • Low Input Capacitance (CI = 1.5 pF Typical).
  • Low Noise.
  • Overshoot and Undershoot < 10% of VCC.
  • Input-Disable Feature Allows Floating Input Conditions.
  • Ioff Supports Partial-Power-Down Mode Operation.
  • Input Hysteresis Allows Slow Input Transition and.

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SN74AUP1G126 Low-Power Single Bus Buffer Gate
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Full PDF Text Transcription

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Product Folder Order Now Technical Documents Tools & Software Support & Community Reference Design SN74AUP1G125 SCES595N – JULY 2004 – REVISED JULY 2017 SN74AUP1G125 Low-Power Single Bus Buffer Gate With 3-State Output 1 Features •1 Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption (ICC = 0.9 µA Maximum) • Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V) • Low Input Capacitance (CI = 1.5 pF Typical) • Low Noise – Overshoot and Undershoot < 10% of VCC • Input-Disable Feature Allows Floating Input Conditions • Ioff Supports Partial-Power-Down Mode Operation • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input • Wide Operating VCC Range of 0.8 V to 3.6 V • 3.
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