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SN74ALVCH16835 - 18-BIT UNIVERSAL BUS DRIVER

General Description

This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE) input.

The device operates in the transparent mode when the latch-enable (LE) input is high.

Key Features

  • Member of the Texas Instruments Widebus™ Family.
  • Operates From 1.65 V to 3.6 V.
  • Max tpd of 3.6 ns at 3.3 V.
  • ±24-mA Output Drive at 3.3 V.
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors.
  • Latch-Up Performance Exceeds 250 mA Per JESD 17.
  • ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A).

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Other Datasheets by Texas Instruments

Part Number Description
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP
SN74ALVCH16825 18-BIT BUFFER/DRIVER
SN74ALVCH16827 20-BIT BUFFER/DRIVER
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH
SN74ALVCH16863 18-BIT TRANSCEIVER
SN74ALVCH162244 16-BIT BUFFER/DRIVER
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com FEATURES • Member of the Texas Instruments Widebus™ Family • Operates From 1.65 V to 3.6 V • Max tpd of 3.6 ns at 3.3 V • ±24-mA Output Drive at 3.3 V • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) DESCRIPTION/ORDERING INFORMATION This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level.