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SN74ALVCH16827 - 20-BIT BUFFER/DRIVER

General Description

This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16827 is composed of two 10-bit sections with separate output-enable signals.

Key Features

  • Member of the Texas Instruments Widebus™ Family.
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process.
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0).
  • Latch-Up Performance Exceeds 250 mA Per JESD 17.
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors.
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Sma.

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Other Datasheets by Texas Instruments

Part Number Description
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP
SN74ALVCH16825 18-BIT BUFFER/DRIVER
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH
SN74ALVCH16863 18-BIT TRANSCEIVER
SN74ALVCH162244 16-BIT BUFFER/DRIVER
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com FEATURES • Member of the Texas Instruments Widebus™ Family • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) • Latch-Up Performance Exceeds 250 mA Per JESD 17 • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DESCRIPTION This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16827 is composed of two 10-bit sections with separate output-enable signals.