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SN65MLVD2 - Single M-LVDS Receivers

General Description

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers.

These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps.

Each receiver channel is controlled by a receive enable (RE).

Key Features

  • Low-Voltage Differential 30-Ω to 55-Ω Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz.
  • SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis.
  • SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions.
  • Wide Receiver Input Common-Mode Voltage Range,.
  • 1 V to 3.4 V, Allows 2 V of Ground Noise.
  • Improved VIT (35 mV).
  • Meets or Exceeds th.

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Other Datasheets by Texas Instruments

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com SINGLE M-LVDS RECEIVERS SN65MLVD2 SN65MLVD3 SLLS767 – NOVEMBER 2006 FEATURES • Low-Voltage Differential 30-Ω to 55-Ω Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz • SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis • SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions • Wide Receiver Input Common-Mode Voltage Range, –1 V to 3.