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SCANPSC100F - Embedded Boundary Scan Controller

Description

The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus.

Features

  • 1.
  • 23 Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture.
  • Supported by Texas Instruments SCAN Ease (Embedded.

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Full PDF Text Transcription

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OBSOLETE SCANPSC100F www.ti.com SNOS134D – SEPTEMBER 1998 – REVISED APRIL 2013 SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support) Check for Samples: SCANPSC100F FEATURES 1 •23 Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture • Supported by Texas Instruments SCAN Ease (Embedded Application Software Enabler) Software • Uses Generic, Asynchronous Processor Interface; Compatible with a Wide Range of Processors and PCLK Frequencies • Directly Supports Up to Two 1149.1 Scan Chains • 16-bit Serial Signature Compaction (SSC) at the Test Data In (TDI) Port • Automatically Produces Pseudo-Random Patterns at the Test Data Out (TDO) Port • Fabricated on FACT™ 1.5 μm CMOS Process • Supports 1149.
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