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SCANPSC110F - SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port

Download the SCANPSC110F datasheet PDF. This datasheet also covers the SCANPSC110 variant, as both devices belong to the same scan bridge hierarchical and multidrop addressable jtag port family and are provided as variant models within a single manufacturer datasheet.

Description

The SCANPSC110F Bridge extends the IEEE Std.

1149.1 test bus into a multidrop test bus environment.

The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules.

Features

  • not described in this datasheet such as 8 slot inputs for enhanced address capability and additional instructions. For a completed.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SCANPSC110_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port Fairchild Semiconductor
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Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
SCAN12100 CPRI SerDes
SCAN16512 Low Voltage Universal 16-bit IEEE 1149.1 Bus Transceiver
SCAN16602 Low Voltage Universal 16-bit IEEE 1149.1 Bus Transceiver
SCAN182245A Non-Inverting Transceiver
SCAN18245T Non-Inverting Transceiver

Full PDF Text Transcription

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SCANPSC110F SCAN Bridge October 1999 SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) General Description The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs.
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