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CDCM1804 - 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

Datasheet Summary

Description

The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution.

The CDCM1804 is specifically designed for driving 50-Ω transmission lines.

Features

  • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output.
  • Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output.
  • Low-Output Skew 15 ps (Typical) for Clock-Distribution.

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Datasheet preview – CDCM1804

Datasheet Details

Part number CDCM1804
Manufacturer Texas Instruments
File Size 2.19 MB
Description 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
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Full PDF Text Transcription

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www.ti.com CDCM1804 SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER FEATURES • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output • Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output • Low-Output Skew 15 ps (Typical) for Clock-Distribution Applications for LVPECL Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise • VCC Range 3 V–3.
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