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74SSTUB32868 - 28-Bit to 56-Bit Registered Buffer

Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation.

One device per DIMM is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM loads.

Features

  • 1.
  • 2 Member of the Texas Instruments Widebus+ â„¢Family.
  • Pinout Optimizes DDR2 DIMM PCB Layout.
  • 1-to-2 Outputs Supports Stacked DDR2 DIMMs.
  • One Device Per DIMM Required.
  • Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption.
  • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line.
  • Supports SSTL_18 Data Inputs.
  • Differential Clock (CLK and CLK) Inputs.

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