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XCR3128XL 128 Macrocell CPLD
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DS016 (v1.8) January 8, 2002
Preliminary Product Specification
Features
• • • • • Lowest power 128 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 128 macrocells with 3,000 usable gates Available in small footprint packages - 144-pin TQFP (108 user I/O pins) - 144-ball CS BGA (108 user I/O) - 100-pin VQFP (84 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.