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W3EG2128M72AFSR-D3 - 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC

Download the W3EG2128M72AFSR-D3 datasheet PDF. This datasheet also covers the W3EG2128M72AFSR-AD3 variant, as both devices belong to the same 2gb - 2x128mx72 ddr sdram registered ecc family and are provided as variant models within a single manufacturer datasheet.

General Description

The W3EG2128M72AFSR is a 2x128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components.

The module consists of thirtysix 128Mx4 components, in FBGA packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock.

Key Features

  • Double-data-rate architecture DDR266, DDR333, and DDR400 Bi-directional data strobes (DQS) Phase-lock loop (PLL) clock driver to reduce loading Differential clock inputs (CK & CK#) ECC error detection and correction Programmable Read Latency 2, 2.5 (clock) Programmable Burst Length (2, 4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank www. DataSheet4U. com.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (W3EG2128M72AFSR-AD3_WhiteElectronic.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number W3EG2128M72AFSR-D3
Manufacturer White Electronic
File Size 298.80 KB
Description 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC
Datasheet download datasheet W3EG2128M72AFSR-D3 Datasheet

Full PDF Text Transcription for W3EG2128M72AFSR-D3 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for W3EG2128M72AFSR-D3. For precise diagrams, and layout, please refer to the original PDF.

White Electronic Designs W3EG2128M72AFSR-D3 -AD3 FINAL* 2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA FEATURES Double-data-rate architecture DDR266, DDR333, and D...

View more extracted text
PLL, FBGA FEATURES Double-data-rate architecture DDR266, DDR333, and DDR400 Bi-directional data strobes (DQS) Phase-lock loop (PLL) clock driver to reduce loading Differential clock inputs (CK & CK#) ECC error detection and correction Programmable Read Latency 2, 2.5 (clock) Programmable Burst Length (2, 4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank www.DataSheet4U.com DESCRIPTION The W3EG2128M72AFSR is a 2x128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components.

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