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VG36648041DT - CMOS Synchronous Dynamic RAM

Download the VG36648041DT datasheet PDF. This datasheet also covers the VG36641641DT variant, as both devices belong to the same cmos synchronous dynamic ram family and are provided as variant models within a single manufacturer datasheet.

Description

4 (word x bit x bank), respectively.

Features

  • Single 3.3V ( ± 0.3V ) power supply.
  • High speed clock cycle time -6 : 166MHz, available only on 4MX16 option -7 : 143MHz, 133MHz -7L: 133MHz -8H: 100MHz.
  • Fully synchronous operation referenced to clock rising edge.
  • Possible to assert random column access in every cycle.
  • Quad internal banks controlled by A12 & A13 (Bank Select).
  • Byte control by LDQM and UDQM for VG36641641D.
  • Programmable Wrap sequen.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (VG36641641DT-VanguardInternationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number VG36648041DT
Manufacturer Vanguard International Semiconductor
File Size 1.00 MB
Description CMOS Synchronous Dynamic RAM
Datasheet download datasheet VG36648041DT Datasheet

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Other Datasheets by Vanguard International Semiconductor

Part Number Description
VG36648041BT-10 CMOS Synchronous Dynamic RAM
VG36648041BT-7 CMOS Synchronous Dynamic RAM
VG36648041BT-8 CMOS Synchronous Dynamic RAM
VG36648041CT CMOS Synchronous Dynamic RAM
VG36641641BT CMOS Synchronous Dynamic RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
VIS Description 4 (word x bit x bank), respectively. VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII. Features • Single 3.3V ( ± 0.
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