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TC74VHCT04AFK - Hex Inverter

Download the TC74VHCT04AFK datasheet PDF. This datasheet also covers the TC74VHCT04AF variant, as both devices belong to the same hex inverter family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: tpd = 4.7 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C.
  • Compatible with TTL inputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
  • Power down protection is provided on all inputs and outputs.
  • Balanced propagation delays: tpLH ≈ tpHL Weight SOP14-P-300-1.27A VSSOP14-P-0030-0.50.
  • Low noise: VOLP = 1.0 V (max).
  • Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc. ) 04 type. : 0.18 g (typ. ) : 0.02 g (typ. ).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74VHCT04AF_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Toshiba

Part Number Description
TC74VHCT04AF Hex Inverter
TC74VHCT04AFN HEX INVERTER
TC74VHCT04AFT HEX INVERTER
TC74VHCT00AF Quad 2-Input NAND Gate
TC74VHCT00AFK Quad 2-Input NAND Gate
TC74VHCT08AF Quad 2-Input AND Gate
TC74VHCT08AFK Quad 2-Input AND Gate
TC74VHCT08AFN QUAD 2-INPUT AND GATE
TC74VHCT08AFT QUAD 2-INPUT AND GATE
TC74VHCT125AF Quad Bus Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74VHCT04AF/AFK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT04AF, TC74VHCT04AFK Hex Inverter The TC74VHCT04A is an advanced high speed CMOS INVERTER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc.