TC74HC40102AF - Dual BCD Programmable Down Counter
Toshiba
Download the TC74HC40102AF datasheet PDF.
This datasheet also covers the TC74HC40102AP variant, as both devices belong to the same dual bcd programmable down counter family and are provided as variant models within a single manufacturer datasheet.
General Description
Count is inhibited regardless of other inputs.
Counter is set to maximum count.
Key Features
High speed: fmax 40 MHz (typ. ) at VCC = 5 V.
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
High noise immunity: VNIH = VNIL = 28% VCC (min).
Output drive capability: 10 LSTTL loads.
Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
Balanced propagation delays: tpLH ∼.
tpHL.
Wide operating voltage range: VCC (opr) = 2 to 6 V.
Pin and function compatible with 40102B, 40103B
Weight DIP16-P-300-2.54A SOP1.
Full PDF Text Transcription for TC74HC40102AF (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
TC74HC40102AF. For precise diagrams, and layout, please refer to the original PDF.
4HC40102AF TC74HC40103AP, TC74HC40103AF TC74HC40102AP/AF Dual BCD Programmable Down Counter TC74HC40103AP/AF 8-Bit Binary Programmable Down Counter The TC74HC40102A and TC74HC40103A are high speed CMOS PROGRAMMABLE DOWN COUNTERS fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The output terminal ( CO/ZD ) goes to an active low state when the down count reaches zero. Since the TC74HC40102A is designed as a BCD counter, programming up to 99 counts is possible. The TC74HC40103A, with its 8-bit binary construction
TC74HC40102AF Datasheet
