Datasheet4U Logo Datasheet4U.com

CXL5002P - CMOS-CCD 1/2H Delay Line for NTSC

Description

The CXL5002M/P are general-purpose CMOS-CCD delay line ICs that provide 1/2H delay time for NTSC.

Features

  • Low power consumption 70mW (Typ. ).
  • Small size package (8-pin SOP, DIP).
  • Low differential gain DG = 3% (Typ. ).
  • Input signal amplitude 180 IRE (= 1.28Vp-p, Max. ).
  • Low input clock amplitude operation 150mVp-p (Min. ).
  • Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits) Functions.
  • 340-bit CCD register.
  • Clock drivers.
  • Autobias circuit.
  • Sync tip clamp circuit.
  • Sam.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CXL02TG3 HIGH PERFORMANCE ACCELEROMETER ACEINNA
CXL04GP1 GENERAL PURPOSE ACCELEROMETER ACEINNA
CXL04GP3 GENERAL PURPOSE ACCELEROMETER ACEINNA
CXL10GP1 GENERAL PURPOSE ACCELEROMETER ACEINNA
CXL10GP3 GENERAL PURPOSE ACCELEROMETER ACEINNA

Other Datasheets by Sony Semiconductor Solutions

Part Number Description
CXL5002M CMOS-CCD 1/2H Delay Line for NTSC
CXL5001M CMOS-CCD 1H Delay Line for NTSC
CXL5001P CMOS-CCD 1H Delay Line for NTSC
CXL5003M CMOS-CCD 1H Delay Line for PAL
CXL5003P CMOS-CCD 1H Delay Line for PAL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CXL5002M/P CMOS-CCD 1/2H Delay Line for NTSC Description The CXL5002M/P are general-purpose CMOS-CCD delay line ICs that provide 1/2H delay time for NTSC. Features • Low power consumption 70mW (Typ.) • Small size package (8-pin SOP, DIP) • Low differential gain DG = 3% (Typ.) • Input signal amplitude 180 IRE (= 1.28Vp-p, Max.) • Low input clock amplitude operation 150mVp-p (Min.
Published: |