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CY2SSTV855 - Differential Clock Buffer/Driver

Description

The CY2SSTV855 is a high-performance, very-low-skew, very-low-jitter zero-delay buffer that distributes a differential clock input pair (SSTL_2) to four differential (SSTL_2) pairs of clock outputs and one differential pair of feedback clock outputs.

Features

  • Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM.

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Full PDF Text Transcription

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CY2SSTV855 Differential Clock Buffer/Driver Features • Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input • SSCG: Spread Aware™ for electromagnetic interference (EMI) reduction • 28-pin TSSOP package • Conforms to JEDEC DDR specifications Functional Description The CY2SSTV855 is a high-performance, very-low-skew, very-low-jitter zero-delay buffer that distributes a differential clock input pair (SSTL_2) to four differential (SSTL_2) pairs of clock outputs and one differential pair of feedback clock outputs.
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