SiS5592 - PCI A.G.P. & CPU Memory Controller

Download the SiS5592 datasheet PDF. This datasheet also covers the SiS5591 variant, as both devices belong to the same pci a.g.p. & cpu memory controller family and are provided as variant models within a single manufacturer datasheet.

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SiS5592 pci a.g.p. & cpu memory controller by Silicon Integrated System - Datasheet Preview — Note: The manufacturer provides a single datasheet file (SiS5591-SiliconIntegratedSystem.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	SiS5592
Manufacturer	Silicon Integrated System
File Size	916.82 KB
Description	PCI A.G.P. & CPU Memory Controller
Datasheet	SiS5592 Datasheet

Other Datasheets by Silicon Integrated System

Part Number	Description
SiS5591	PCI A.G.P. & CPU Memory Controller
SIS5595	Pentium PCI System I/O
SiS5596	PCI Memory & VGA Controller
SIS550	SoC
SIS5501	PCI/ISA Cache Memory Controller
SIS5502	PCI Local Data Buffer
SIS5503	PCI System I/O
SIS551	SoC
SiS5511	PCI/ISA Cache Memory Controller
SiS5512	PCI Local Data Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SiS5591/5592 Pentium PCI A.G.P. Chipset 1. SiS5591/5592 SiS5595 OVERVIEW SiS5591/5592 SiS5595 PCI A.G.P. & CPU Memory Controller PCI SYSTEM I/O The SiS5591/5592 SiS5595 glueless P5 A.G.P. chipset provides a high performance/cost index Desktop/Mobile solution for the Intel Pentium P54C/P55C, AMD K5/K6, and Cyrix M1/M2 A.G.P. system. The SiS5591/SiS5592 A.G.P./PCI controller integrated the Host-to-PCI bridge, the L2 cache controller, the DRAM controller, the Accelerated Graphics Port interface, and the PCI IDE controller. The L2 cache controller can support up to 1 M P.B. SRAM, and the DRAM controller can support EDO/FP/SDRAM memory up to 768 MB with optional ECC or parity check function. The A.G.P. 1.